Field of the Invention
The present invention relates to an image processing apparatus that performs image processing on image data, a control method and a storage medium that stores a computer program.
Description of the Related Art
In recent years, controllers for performing device control within an MFP (multifunctional peripheral) that are constituted by a high-speed general-purpose CPU and an image processing control CPU are known. In such a configuration, the general-purpose high-speed CPU performs general-purpose interface control of a network or the like and job sequence control, for example. Also, the image processing control CPU performs control of a document reading apparatus (scanner) and image processing control, for example. A print function and a scan function of the MFP are executed by the general-purpose high-speed CPU and the image processing control CPU operating in tandem.
There are cases where different image processing is required per page when executing a scan job. For example, the MFP may be configured to detect the presence of foreign particles between pages by reading the white plate or the document guide plate (Japanese Patent Laid-Open Nos. 2002-176542 and 2006-173933). In this case, whether or not to perform pixel correction corresponding to the position of foreign particles is determined on a page-by-page basis, according to the presence of foreign particles.
Also, the MFP may, for example, be configured to detect whether a page is achromatic or chromatic before performing document reading (Japanese Patent Laid-Open No. 2005-184101). In this case, whether to perform achromatic image processing or chromatic image processing is determined for the next page on a page-by-page basis, according to whether the page is achromatic or chromatic.
Also, the MFP may, for example, be configured to read consecutive pages using an ADF (Auto Document Feeder). Depending on factors such as the structure of the ADF and the attachment orientation of the sensor, the reading direction may be reversed between the front and back sides of the page; that is, the image data that is obtained may be a mirror image of the original. In this case, mirror image correction for correcting the mirror image to the correct image needs to be performed on the image data of whichever of the front or back side is the mirror image.
Also, the types of reading devices that are used in MFPs include CCD image sensors, CMOS image sensors, and contact image sensors (CISs). Technology for improving the reading speed by installing two of these reading devices for respectively reading the front side and back side is known. At this time, different reading devices may be installed for reading the front and back sides, such as a CMOS image sensor for the front side and a CIS for the back side. In the case of such a configuration, circuits that correct for issues particular to CISs such as inter-chip missing pixels (Japanese Patent Laid-Open No. 2003-348336) and resolution degradation (Japanese Patent Laid-Open No. 2002-199222) will be required in the image processing for the back side of the page only.
On the other hand, devices such as programmable logic devices (PLDs) and FPGAs (Field Programmable Gate Arrays) that are capable of reconfiguring internal logic circuits are known. Generally, PLDs and FPGAs are capable of switching the function of an internal logic block by writing logic circuit configuration information stored in a nonvolatile memory such as ROM to a configuration memory, which is an internal volatile memory, at the time of startup. Also, because information in the configuration memory is cleared at the time of power off, reconfiguration is performed by writing the logic circuit configuration information to the configuration memory again at the time of power on. A method for thus configuring a hardware resource only once is called static reconfiguration.
Also, a technique for loading configuration data to an FPGA via a general-purpose high speed bus such as PCIe (PCI-Express) that is connected to the FPGA, according to computational processing of an accelerator, with the CPU as the master device, is known (Japanese Patent Laid-Open No. 2013-98823). Such methods for changing the logic circuit during device operation are referred to as dynamic reconfiguration by CPU.
By applying a device capable of dynamic reconfiguration by CPU to the system of an MFP in which a general-purpose high-speed CPU and an image processing CPU operate in tandem, it is conceivable to, for example, add a function that enables the contents of image processing on image data to be changed on a page-by-page basis. However, in order to apply a device capable of dynamic reconfiguration by CPU to the system of an MFP in which a general-purpose high-speed CPU and an image processing CPU operate in tandem, a configuration that controls image processing by coordinating dynamic reconfiguration by the CPU with jobs is required. Although Japanese Patent Laid-Open No. 2013-98823 describes a system that is configured to load configuration data to an FPGA, there is no mention of controlling image processing through coordination with jobs.